1. Field of the Invention
Exemplary embodiments of the present invention relate to a block matching apparatus, and more particularly, to a block matching apparatus, in which a normal driving power and a low driving power are alternately applied to an absolute difference calculation unit for calculating an absolute difference between a pixel of a first image frame and a pixel of a second image frame corresponding thereto among two stereo image frames, and a low absolute difference of corresponding pixels calculated using the low driving power is compensated with a high absolute difference of adjacent corresponding pixels calculated using the normal driving power, so that since a separate estimation unit does not need to be provided, the block matching apparatus can be lightly manufactured in terms of hardware and can reduce power consumption.
2. Description of Related Art
Since a stereo image is an image of an object photographed from different positions at the same moment, a lot of redundant information appears between two image frames, i.e., a left-side image frame and a right-side image frame. Accordingly, compression efficiency can be enhanced by removing such redundancy.
Motion estimation and compensation is used to reduce temporal redundancy between consecutive image frames in an existing two-dimensional image. In the case of a stereo image frame, spatial redundancy similar to the temporal redundancy in the existing two-dimensional image frame also exists between the left-side image frame and the right-side image frame. Such spatial redundancy can be removed using disparity estimation and compensation. The disparity estimation and compensation is performed through a process of setting either the left-side image frame or the right-side image frame as a reference image frame, independently encoding the reference image frame, and then estimating the other image frame in the unit of a block based on the encoded reference image frame.
Blocking matching refers to searching for a unit block matching to the unit block of the reference image frame from the other image frame, and a block having a minimum difference between the unit block of the reference image block and the unit block of the other image frame is searched from the other image frame. Here, the unit block having a minimum difference between the unit block of the reference image block and the unit block of the other image frame is calculated using a sum of absolute difference (SAD).
FIG. 1 is a functional block diagram showing a conventional block matching apparatus in accordance with the prior art.
The conventional block matching apparatus in accordance with the prior art will be described hereinafter in more detail with reference to FIG. 1.
When a matching block is searched from two image frames using a 4×4 unit block, a bit value is input into the compensation absolute difference calculation unit 10 for each of sixteen pixels constituting the 4×4 unit block of a first image frame, i.e., a reference image frame, and each of sixteen pixels constituting the 4×4 unit block of a second image frame, i.e., the other image frame. For example, a first pixel of the first image frame and a first pixel of the second image frame corresponding thereto are input into the compensation absolute difference calculation unit 1, and a second pixel of the first image frame and a second pixel of the second image frame corresponding thereto are input into the compensation absolute difference calculation unit 2. Like this, all the pixels constituting the 4×4 unit block of the first image frame and all the corresponding pixels constituting the 4×4 unit block of the second image frame are input into the compensation absolute difference calculation units respectively assigned to each pixel.
The compensation absolute difference calculation unit (CADCU) 10 calculates a compensation absolute difference between bit values of a pixel of the first image frame and a pixel of the second image frame corresponding thereto based on the bit values of the pixel of the first image frame and the pixel of the second image frame corresponding thereto. The matching unit 20 calculates a sum of the compensation absolute difference of each pixel unit calculated by each compensation absolute difference calculation unit, and determines a unit block having a minimum sum among the unit blocks of the second image frame as the matching block.
FIG. 2 more specifically shows a compensation absolute difference calculation unit of a conventional block matching apparatus in accordance with the prior art.
Referring to FIG. 2, the compensation absolute difference calculation unit 10 includes an absolute difference calculation unit (ADaCU) 11, an estimation unit 13 and a compensation unit 15.
When bit values of a pixel of the first image frame and a pixel of the second image frame corresponding thereto are input into the absolute difference calculation unit 11, the absolute difference calculation unit 11 calculates an absolute difference (AD) between the pixel values of the pixel of the first image frame and the pixel of the second image frame corresponding thereto using the following Equation 1. Generally, the pixel values of the pixel of the first image frame and the pixel of the second image frame are represented in eight bits.AD=|PRi−PLi|  [Equation 1]
wherein PRi denotes a pixel value of a pixel of the first image frame Ri, and PLi denotes a pixel value of a pixel of the second image frame Lj corresponding to the pixel of the first image frame Ri.
The block matching process requires the largest amount of computation and consumes a large amount of power in encoding a stereo image, and a driving power lower than a normal driving power is applied to the absolute difference calculation unit 11 in order to reduce the power consumption in the block matching process. Since a lower driving power is applied to the absolute difference calculation unit 11, an error may occur in the absolute difference between the pixel values of the pixel of the first image frame and the pixel of the second image frame corresponding thereto calculated by the absolute difference calculation unit 11, and the estimation unit 13 applied with a normal driving power estimates and compensates the error in the absolute difference occurring at the absolute difference calculation unit 11. The estimation unit 13 calculates an estimated absolute difference using only some upper bits of the eight bits representing the pixel values of the pixel of the first image frame and the pixel of the second image frame corresponding thereto in order to reduce the power consumption and the amount of computation.
The compensation unit 15 compares the absolute difference calculated by the absolute difference calculation unit 11 with the estimated absolute difference calculated by the estimation unit 13, and determines that the absolute difference calculated by the absolute difference calculation unit 11 does not have an error if the absolute difference calculated by the absolute difference calculation unit 11 is equal to the estimated absolute difference calculated by the estimation unit 13. On the contrary, if the absolute difference calculated by the absolute difference calculation unit 11 is different from the estimated absolute difference calculated by the estimation unit 13, the upper bits of the absolute difference calculated by the absolute difference calculation unit 11 are compensated with bit values of the estimated absolute difference calculated by the estimation unit 13.
The conventional blocking matching apparatus as described above can reduce the power consumed for block matching by applying a lower driving power to the absolute difference calculation unit 11. However, such a conventional blocking matching apparatus entails a problem in that since the estimation unit 13 and the compensation unit 15 for estimating and compensating an error occurred in the absolute difference calculated by the absolute difference calculation unit 11 should be provided in each compensation absolute difference calculation unit, the number of hardwares of the blocking matching apparatus increases and each compensation absolute difference calculation unit consumes a large amount of power to estimate the error in the absolute difference.